The present invention relates generally to enhancement-mode field effect transistor (ENFET) logic circuits, and more particularly to ENFET logic circuits which are current driven to provide for greater fan-out capability.
Heretofore, enhancement-mode field effect transistor logic circuits have been based on a common-source inverter configuration. This particular inverter design has poor fan-out capability due to the high level of gate current which exists in the device when a logic high input signal is applied thereto. Fan-out refers to the number of circuits which may be connected to the output of one particular logic circuit and which may be driven thereby. The design of high-level logic circuits requires that the devices used therein have relatively high fan-out ratios. In certain circumstances it is impossible for a single ENFET inverter circuit to drive even two additional circuits.
Conventional ENFET circuits are described in publications entitled "High Speed GaAs Integrated Circuits," by Steven I. Long et al, Proceedings of the IEEE, Vol. 70, No. 1, January 1982, and "Design and Performance of GaAs Normally-Off MESFET Integrated Circuits," by Katsuhiko Suyama et al, IEEE Transactions on Electron Devices, Vol. ED 27, No. 6, June 1980.
Accordingly, it would be an improvement in the art to have an enhancement-mode ENFET logic circuit design which allows for greater fan-out capability.